1. Technical Field
Several aspects of the present invention relates to a method for manufacturing a semiconductor device, in particular, a technique to prevent an etching selectivity of SiGe with respect to Si from deteriorating.
2. Related Art
A field-effect transistor formed on a silicon-on-insulator (SOI) substrate has been drawing attention recently because of its usability in terms of easy-element isolation, latch-up free, and small source/drain junction capacitance. Especially, since a fully depleted SOI transistor enabling low power consumption and high-speed operation is easy to drive at a low voltage, researches to drive an SOI transistor in a fully depleted mode are actively carried out. A method capable of manufacturing an SOI transistor economically by forming an SOI layer on a bulk substrate (i.e. Separation by Bonding Si islands (SBSI) is disclosed In JP-A-2005-354024 and Separation by Bonding Si islands (SBSI) for LSI Applications. (T, Sakai et al.), Second International SiGe Technology and Device Meeting, Meeting Abstract, pp. 230-231, May (2004). In SBSI, after Si and SiGe layers are formed on a Si substrate, only the SiGe layer is selectively removed by using a difference in etching rates between Si and SiGe so as to form, a cavity between the Si substrate and the Si layer. Then, a SiO2 layer is embedded between the Si substrate and the Si layer by thermally oxidizing the Si exposed in the cavity, forming a BOX layer between the Si substrate and the Si layer.
In the SBSI described above, a process to selectively remove a SiGe layer is important to obtain a stable process yield and a high yield of electric characteristics. In a manufacturing method in related art, a logic circuit and a memory circuit have a plane pattern of an active layer (SOI layer) that is less various in size and density, thereby providing a stable process yield and electric characteristics.
However, in a circuit, having a bulk silicon device and an SOI device mounted in combination, and in a circuit including devices having various driving voltages and being mounted in combination, differences in area and density between plane patterns of the SOI layers are generally large. Here, in the manufacturing method in related art, an etching speed of SiGe layer is deteriorated (that is slowed down) depending on a spot due to high or low density of the patterns. Further, especially, when an etching time is longer, an etching speed of Si becomes faster.
That is, in the manufacturing method in related art, when a semiconductor having various devices such as a bulk silicon device and an SOI device mounted in combination is manufactured, an etching selectivity of a SiGe layer with respect to a Si layer is partially deteriorated. Therefore, it is hard to form an SOI layer with a large area having a stable shape and an even film thickness, or an SOI layer into various shapes with high yields. As the above, the manufacturing method in related art has been required to improve a process yield and stabilize electrical characteristics of a semiconductor having various devices described above mounted in combination.